Random Access Memory (RAM) cells are well known in the art. Many RAM cells are optimized for frequent programming and rapid access times. The present invention is directed toward applications where these conditions are not critical. For example, in many programmable logic devices, RAM cell access times are not critical and the RAM cells are not programmed frequently.
FIG. 1 illustrates three prior art RAM cells 20A, 20B, and 20C in a First-In-First-Out (FIFO) configuration. Each RAM cell 20 includes a forward inverter 22 and a feedback inverter 24 collectively operating to store a single binary digit (bit). An address line (ADD) is associated with each RAM cell 20. Each address line is used to control an access transistor T.
The circuit of FIG. 1 operates in a FIFO manner because each RAM cell is driven by the RAM cell before it. For example, during programming, the address line (ADD.sub.-- 1) for RAM cell 20B is driven high, turning-on access transistor T1. As a result, the bit stored in RAM cell 20A is written into RAM cell 20B. This process is repeated until the bit is written to the desired RAM cell of the series string of RAM cells.
There are a number of problems with a FIFO RAM cell of the type shown in FIG. 1. One drawback is that it requires a relatively high supply voltage. That is, to successfully write a logical zero onto an output node of a destination cell, a logical one needs to be written into the destination cell from a source cell. For example, to obtain a logical zero at the output of destination cell 20C, a logical one must be written to the input of the cell. To insure a sufficient trip voltage for the inverter 22C, a relatively large voltage must be generated by the source cell 20B to overcome the voltage drop associated with the access transistor T2 at the input of the destination cell 20C.
Another problem with the prior art device of FIG. 1 is that it is relatively space intensive. The feedback inverter 24 of each cell 20 is a weak device with a relatively large channel length. The access transistors T are relatively conductive devices with relatively larger widths. These geometries require a relatively large amount of die area.
Another problem associated with the prior art device of FIG. 1 is its susceptibility to noise. A noise glitch on an address line (ADD) may turn on an access transistor T, resulting in a cell being overwritten by a previous serial cell. For example, a noise glitch on address line ADD.sub.-- 1 may turn on access transistor T1, causing a logical one from cell 20A to be written over a logical zero at the input of cell 20B.
In view of the foregoing, it would be highly desirable to develop a RAM cell that is noise-immune, compact, and does not require a large supply voltage.